A cache is a memory bank that bridges main memory and a processing core, and is used to speed up data transfers and instruction execution. The cache is usually faster than main memory and allows instructions to be executed and data to be read and written at relatively higher speed. A suitable type of random access memory (RAM) (e.g., a static RAM or SRAM) may be used as a cache.
A second level cache may be shared among two or more processing cores and may include different classes of storage areas (referred henceforth as cache resources) for storing different types of information that is related to data or instructions, e.g., tag memory, dirty memory, valid memory, data memory, error correcting code (ECC) memory, etc. A cache is usually also associated with one or more other elements (also referred henceforth as cache resources) that are used, for example, for generating, checking, and/or correcting error correcting codes associated with data stored in the cache, e.g., ECC check module, ECC correcting module, ECC generation module, etc. A cache may handle many different types of cache commands (e.g., read access command, write access commands, snoop commands, etc.), which access the cache to read data from and/or to write data to the cache.
Processing a cache command may require access to one or more of the cache resources. However, in a shared cache environment access to the one or more cache resources may be limited to a single processing core until a cache command has been resolved. For example, if a tag memory of a cache is being accessed by a first processing core for processing a first cache command, the tag memory may not be accessed by a different processing core (or by the same processing core) for processing a different cache command until resolution of the first cache command (or at least a part of the first cache command). This may be a limiting factor in achieving higher speed of a cache, particularly when the cache is shared by two or more processing cores.
A cache command may either be a hit or a miss. For example, a cache command may include data associated with an address of an external memory. If data associated with the address resides within the cache and is valid (e.g., is in synchronization with an external memory), the command is a hit. On the other hand, if data associated with the address does not reside within the cache and/or is dirty (e.g., is not in synchronization with an external memory), the command is a miss. If a cache command is a miss, one or more data bytes from the cache may need to be evicted to make space for new data to be fetched from the external memory (e.g., data associated with the cache command is to be fetched from the external memory). In a conventional cache, determining whether a cache command is a hit or a miss, and accessing data from or writing data to the cache (in case the cache command is a hit) or accessing data from the cache for eviction (in case the cache command is a hit) is usually time consuming. For example, start of processing of a cache command may not commence in a conventional cache until a hit/miss determination of a previous command is made, and/or until processing of the previous command is fully (or at least partially) completed.